收稿日期: 2009-06-06
修回日期: 2009-07-17
网络出版日期: 2010-01-15
Design of a twisting-style switch matrix based on bus architecture
Received date: 2009-06-06
Revised date: 2009-07-17
Online published: 2010-01-15
孙嘉斌 , 杨海钢 . 一种基于总线结构的扭转型交叉开关矩阵[J]. 中国科学院大学学报, 2010 , 27(1) : 43 -48 . DOI: 10.7523/j.issn.2095-6134.2010.1.006
A novel twisting-style switch matrix is proposed based on the research into architectures of traditional switch matrixes. By using the method of wire twisting, a single tileable switch cell can be replicated and abutted to form the layout of switch matrix. SPICE simulation demonstrates that the proposed switch matrix presents uniform delay characteristic and lower static power dissipation.
Key words: FPGA; switch matrix; wire twisting; tileable
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