收稿日期: 2010-03-31
修回日期: 2010-04-16
网络出版日期: 2010-09-15
基金资助
国家高技术研究发展计划(863)项目(2007AA12Z123)资助
Optimization of digital PID controller on hardware
Received date: 2010-03-31
Revised date: 2010-04-16
Online published: 2010-09-15
蔡晓宁 , 陈仲林 , 董戈 , 谢珊英 . 数字PID控制器的硬件优化设计[J]. 中国科学院大学学报, 2010 , 27(5) : 690 -694 . DOI: 10.7523/j.issn.2095-6134.2010.5.017
PID control method is widely used in the feed-back circuit of switch mode power supply. Since the analog PID controller is sensitive to temperature and electromagnetic interference, we discuss hardware implementation of digital PID controller in the present paper. With pipeline operation the efficiency of the algorithm was improved, and with signed binary fraction operation the resource cost of the circuit was reduced. Finally, this digital PID algorithm was implemented on an Actel AFS600 FPGA chip, and simulation result shows its efficiency and feasibility.
Key words： digital PID controller; FPGA; AFS600; pipeline; SBF
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