收稿日期: 2009-12-09
修回日期: 2010-05-11
网络出版日期: 2010-11-15
基金资助
国家"863"项目(2007AA12Z344)资助
A Σ-Δ fractional-N frequency synthesizer with low in-band phase noise
Received date: 2009-12-09
Revised date: 2010-05-11
Online published: 2010-11-15
为使Σ-Δ小数频率合成器获得低带内相位噪声,在设计中调制器采用一种5阶4bit输出的单环Σ-Δ调制器,比3阶MASH(Multi-stAge noise-SHaping)结构有着更低的带内量化噪声.一款具有低带内相位噪声和快速锁定特点的2.6GHz Σ-Δ小数频率合成器在0.25μm CMOS工艺中实现.测试结果显示,该频率合成器在40KHz频率偏移处相噪-86.5dBc/Hz,杂散小于-65dBc.在2.5V的电源供电下,电流为25.5mA,整个芯片面积3.9mm2(核心电路面积0.63mm2).
于云丰 , 叶甜春 , 马成炎 , 乐建连 , 甘业兵 . 低相位噪声Σ-Δ小数频率合成器[J]. 中国科学院大学学报, 2010 , 27(6) : 782 -787 . DOI: 10.7523/j.issn.2095-6134.2010.6.008
In order to achieve low in-band phase noise in Σ-Δ fractional-N frequency synthesizers, a 5th-order 4bit Σ-Δ modulator is used to replace a 3rd-order MASH modulator. A 2.6GHz Σ-Δ fractional-N frequency synthesizer with low in-band phase noise and fast-locking characteristics was implemented in 0.25μm CMOS process. The measurement results show that the in-band phase noise of this synthesizer is -86.5dBc/Hz (at 40KHz offset), and all the spurs are less than - 65dBc. The whole synthesizer excluding the Σ-Δ modulator consumes 25.5mA in the case of 2.5V supply, and it occupies 3.9mm2(with a core area of 0.63mm2).
Key words： Σ-Δ modulator; frequency synthesizer; MASH; CMOS; PLL
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