提出一种应用于FPGA中的新型宽调整范围的数字占空比矫正电路. 该电路在0.13 μm CMOS标准工艺下实现,具有固定上升延时的特性. 通过采用连续逼近寄存器,实现了占空比的快速调整. 测试结果表明,其调整范围为10%~85%,在80~250 MHz输入范围内输出占空比变化为50％±2％,所需调整时间为6个时钟周期.
A novel all-digital CMOS duty-cycle-correction (DCC) circuit with wide correction ranges of input duty cycle is proposed in FPGA. The proposed DCC circuit has the fixed rising edge. A successive approximation register circuit is utilized to reduce the adjusting time of the DCC. The proposed circuit is fabricated in a 0.13 μm CMOS standard technology. Measurement results show that the DCC adjusts the output duty cycle to 50%±2% for a wide input duty cycle range from 10% to 85%. The DCC could operate within a frequency range from 80 MHz to 250 MHz with the adjusting time of 6 clock cycles.
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