提出一种支持动态搜索区域的可变块大小运动估计硬件结构, 弥补固定大小搜索区域的不足, 可同时降低外存带宽、计算复杂度和功耗. 使用循环分布式存储结构来支持动态搜索区域的数据存取. 此外, 对耗时的SAD(sum of absolute differences)计算阵列进行均衡的流水线划分和加法逻辑优化. 实现结果表明, 相比同类设计, 该设计以少量的吞吐率损失, 换取面积效率和功耗效率的明显提高.
A VBSME with dynamic search range is proposed to overcome the defects of the engine with fixed search range, and it reduces off-chip bandwidth, computational complexity, and power dissipation. A circularly distributed storage structure is adopted to realize the access to the dynamic search area. Besides, the time-consuming SAD computing array is divided into the balanced and adder-optimized pipelines. The implementation results show that, compared to traditional engines, the proposed engine can achieve significant improvements of the hardware and the power efficiency without much loss of throughput.
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