收稿日期: 2011-12-23
修回日期: 2012-04-23
网络出版日期: 2012-04-23
基金资助
国家973计划(2011CB302501)、国家863计划(2012AA010902,2012AA010901)、国家科技重大专项(2009ZX01036-001-002,2011ZX01028-001-002-3)和国家自然科学基金(60970023)资助
FTPA: a flexible chip multiprocessor architecture with configurable cores
Received date: 2011-12-23
Revised date: 2012-04-23
Online published: 2012-04-23
孙涛 , 安虹 , 毛梦捷 , 任永青 , 王涛 , 张海博 . FTPA:一种具有可配置核的灵活多核处理器结构[J]. 中国科学院大学学报, 2013 , 30(2) : 257 -263 . DOI: 10.7523/j.issn.1002-1175.2013.02.018
Nowadays, most chip multiprocessor (CMP) designs face the challenge of how to keep the balance between on-chip parallelism, communication overhead, program performance, and resource utilization. By using the conception of physical core and logical processor, flexible-core CMPs(FCMPs) provide more optimization space. We propose a novel FCMP architecture named FTPA (flexible tiled processor architecture), which provides an efficient platform for single thread execution. The evaluation demonstrates that FTPA outperforms the state-of-art FCMP design, TFlex, by 19.2% on average.
[1] Hill M D, Marty M R. Amdahl's law in the multicore era[J]. IEEE Computer, 2008, 41(7): 33-38.
[2] Sherwood T, Perelman E, Hamerly G, et al. Discovering and exploiting program phases[J]. IEEE Micro, 2003, 23(6): 84-93.
[3] Ipek E, Kirman M, Kirman N, et al. Core fusion: accommodating software diversity in chip multiprocessors[C]//Tullsen D (ed). Proceedings of ISCA'07. New York: ACM Press, 2007: 186-197.
[4] Tarjan D, Boyer M, Skadron K. Federation: boosting per-thread performance of throughput-oriented manycore architectures[J]. ACM Transactions on Architecture and Code Optimization, 2010, 7(4): (article 19)1-38.
[5] Zhong H, Lieberman S A, Mahlke S A. Extending multicore architectures to exploit hybrid parallelism in single-thread applications[C]//Louri A (ed). Proceedings of HPCA'07. Washington: IEEE CS, 2007: 25-36.
[6] Watanabe Y, Davis J D, Wood D A. WiDGET: wisconsin decoupled grid execution tiles[C]//Seznec A(ed). Proceedings of ISCA'10. New York: ACM Press, 2010: 2-13.
[7] Kim C, Sethumadhavan S, Govindan M, et al. Composable lightweight processors[C]//Bellas N (ed). Proceedings of MICRO'07. Washington: IEEE CS, 2007: 381-394.
[8] Gulati D, Kim C, Sethumadhavan S, et al. Multitasking workload scheduling on flexible-core chip multiprocessors[C]//Moshovos A(ed). Proceedings of PACT'08. New York: ACM Press, 2008: 187-196.
[9] Gebhart M, Maher B A, Coons K E, et al. An evaluation of the TRIPS computer system[C]//Soffa M L (ed). Proceedings of ASPLOS'09. New York: ACM Press, 2009: 1-12.
[10] Burger D, Keckler S, McKinley K, et al. Scaling to the end of silicon with EDGE architectures[J]. IEEE Computer, 2004, 37(7): 44-55.
[11] Mahlke S A, Lin D C, Chen W Y, et al. Effective compiler support for predicated execution using the hyperblock[C]//Hwu W (ed). Proceedings of MICRO'92. Washington: IEEE CS, 1992: 45-54.
[12] Ranganathan N, Burger D, Keckler S W. Analysis of the TRIPS prototype block predictor[C]//Tullsen D(ed). Proceedings of ISPASS'09. Washington: IEEE CS, 2009: 195-206.
[13] Robatmili B, Coons K E, Burger D, et al. Strategies for mapping data flow blocks to distributed hardware[C]//Gonzalez A (ed). Proceedings of MICRO'08. Washington: IEEE CS, 2008: 23-34.
[14] Chaudhry, Cypher S, Ekman R, et al. ROCK: A high-performance SPARC CMT processor[J]. IEEE Micro, 2009, 29(2): 6-16.
[15] Ren Y, An H, Sun T, et al. Dynamic resource tuning for flexible core chip multiprocessors[C]//Hus C (ed). Proceedings of ICA3PP'10. Heidelberg: Springer-Verlag Berlin, 2010: 32-41.
[16] University of Massachusetts. Scale Compiler Toolset. http://www.cs.utexas.edu/users/cart/Scale/index.html.
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