关键词: 寄存器传输级(RTL), 有限状态机, 自动测试向量产生(ATPG), 时延测试, 故障诊断

Abstract:

The growing complexity of modern ICs is driving the trend of automatic test pattern generation (ATPG) towards testing at high level, particularly at register transfer level (RTL). At the same time, it is also more critical to perform delay testing to ensure correct temporal behavior of fast digital systems than before. This dissertation first surveys the recent development of test generation and delay testing techniques. Then, a new level of description on RTL behavioral model, termed behavioral phase clustering description, is introduced. Techniques of test generation based on behavioral phase clustering descriptions are proposed, and applied to an RTL ATPG system called ATCLUB. Experimental results show that ATCLUB reduces CPU time and test length significantly compared with other ATPG systems. This dissertation also introduces a novel method of delay testing with variable double observations. And a new approach to delay fault diagnosis based on the method is proposed. These techniques are adopted in DTwDO, a delay testing system based on variable double observations, including a ATPG tool and a fault diagnosis tool. Experimental results demonstrate a significant reduction of the number of paths to be selected to guarantee a complete delay testing, and a high rate of successful fault location.

Key words: register transfer level (RTL), finite state machine (FSM), automatic test pattern generation (ATPG), delay testing, fault diagnosis