Interpolation-based anti-jamming E-D-gate DS-SS code tracking architecture
Received date: 2008-09-17
Revised date: 2009-03-02
Online published: 2009-07-15
田宇 , 李国通 , 杨根庆 . 抗干扰插值迟早门扩频跟踪构架[J]. 中国科学院大学学报, 2009 , 26(4) : 513 -516 . DOI: 10.7523/j.issn.2095-6134.2009.4.012
DS-SS is widely used in LEO satellite communication. Since jamming exists in UHF/VHF wave band, which is commonly selected by LEO communication system, anti-jamming module is necessary in receivers. To control the power consuming, an interpolation-based one-sample-per-chip receiver architecture is developed. Performance analyses show that this architecture cuts off half of anti-jamming module computation burden at the cost of the SNR lose less than 0.1dB. By this approach, computation burden and power consuming can be reduced remarkably.
Key words： interpolation; E-D-gate; anti-jamming; low-power-consuming
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