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中国科学院大学学报 ›› 2009, Vol. 26 ›› Issue (4): 513-516.DOI: 10.7523/j.issn.2095-6134.2009.4.012

• 论文 • 上一篇    下一篇

抗干扰插值迟早门扩频跟踪构架

田宇, 李国通, 杨根庆   

  1. 中国科学院微小卫星联合重点实验室, 上海 200050
  • 收稿日期:2008-09-17 修回日期:2009-03-02 发布日期:2009-07-15

Interpolation-based anti-jamming E-D-gate DS-SS code tracking architecture

TIAN Yu, LI Guo-Tong, YANG Gen-Qing   

  1. Shanghai Micro-Sat Joint Key Laboratory, Chinese Academy of Sciences, Shanghai 200050, China
  • Received:2008-09-17 Revised:2009-03-02 Published:2009-07-15

摘要:

为了降低接收机功耗,提出一种基于插值的单倍采样接收机架构. 性能分析显示,在具备成形滤波器的情况下,此构架仅以不足0.1dB的损失为代价,将抗干扰计算量降低了一半,从而极大地降低了接收机计算负担和整体功耗.

关键词: 插值, 迟早门, 抗干扰, 低功耗

Abstract:

DS-SS is widely used in LEO satellite communication. Since jamming exists in UHF/VHF wave band, which is commonly selected by LEO communication system, anti-jamming module is necessary in receivers. To control the power consuming, an interpolation-based one-sample-per-chip receiver architecture is developed. Performance analyses show that this architecture cuts off half of anti-jamming module computation burden at the cost of the SNR lose less than 0.1dB. By this approach, computation burden and power consuming can be reduced remarkably.

Key words: interpolation, E-D-gate, anti-jamming, low-power-consuming

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