为了满足空间遥感相机电子学系统的功能验证需求,设计了一套由FPGA和DDR2 SDRAM等组成的空间遥感相机模拟源系统. 针对DDR2 SDRAM在设计时的难度,从提高信号完整性出发,对DDR2 SDRAM的阻抗匹配形式和匹配电阻位置进行详细分析,并对PCB布局布线及FPGA管脚约束设计给出可行性设计方案. 实验结果表明,按照提出的设计方法,DDR2 SDRAM不论采用单端或差分时钟工作,均可保证数据以320 Mbps/pin来传输,信号质量依然理想.
In order to meet the function verification requirements of the space remote sensing camera electronics system, we design a set of simulator system composed of FPGA and DDR2 SDRAM. For considering difficulties in designing DDR2 SDRAM and for improving the signal integrity, we analyze the DDR2 SDRAM impedance matching form and matching resistance location in detail and give a feasible design scheme on PCB layout and FPGA pin constraints. Experimental results show that DDR2 SDRAM works at data transmission speed of 320 Mbps/pin with either single-ended or differential clock, and the signal quality is still satisfactory.
[1] Yue T. The achievements and future prospects of Chinese space optical remote sensing technology[J]. Spacecraft Recovery and Remote Sensing, 2008,29(3):16-17 (in Chinese). 岳涛.中国航天光学遥感技术成就与展望[J]. 航天返回与遥感, 2008,29(3):16-17.
[2] Xiao L, Wan M, Li T. Research and implementation of a high speed digital image data[J]. Spacecraft Recovery and Remote Sensing, 2009,30(2):50-51 (in Chinese). 肖龙,万旻,李涛.高速数字图像数据传输的研究及实现[J].航天返回与遥感, 2009,30(2):50-51.
[3] Wu C R, Cen F, Cai H Z. Analysis of signal integrity for interconnection between FPGA and DDR2 SDRAM[J]. Computer Engineering and Applications, 2011,47(29):158-160 (in Chinese). 吴长瑞,岑凡,蔡惠智.FPGA与DDR2 SDRAM互联的信号完整性分析[J]. 计算机工程与应用, 2011,47(29):158-160.
[4] Zheng W M,Wang Z S,Shen H H. PCB level SI simulation based on IBIS model for high-speed FPGA system[C]//The Ninth International Conference on Electronic Measurement & Instruments(ICEMI). 2009.
[5] Brennan C, Tudor C, Schroeter E, et al. Signal integrity and PCB layout considerations for DDR2 SDRAM-800 Mb/s and DDR3 memories [EB/OL].[2012-07-15]. http://www.cadence.com/rl/Resources/technical_papers/stp_cdnlives2007_ddr3.pdf.
[6] Johnson H. 高速数字电路设计[M]. 沈立,等,译. 北京:电子工业出版社,2011:5-7.
[7] Bogatin E. 信号完整性分析[M]. 李玉山,李丽平,译. 北京:电子工业出版社,2010:165-169.
[8] Micron 2GB DDR2 SDRAM datasheet. Micro technology inc[EB/OL].(2006)[2013-07-15]. http://www.micron.com/~/media/Documents/Products/Data%20Sheet/DRAM/ 2Gb_DDR2.pdf.
[9] 周润景,袁伟亭,张鹏飞.Cadence 高速电路板设计与仿真[M]. 3版. 北京:电子工业出版社,2009:447-461.
[10] Banas D. Virtex-5 DDR2 memory interface signal integrity design[J]. Electronic Design & Application World for Design and Application Engineers Nikkei Electronics China, 2008(4):84-85.
[11] Xilinx memory interface generator(MIG) user guide[EB/OL].UG086 (v2.3) September 19, 2008:479-480.[2013-07-15].http://www.xilinx.com/support/documentation/user_guides/ug086.pdf.
[12] 田耘,徐文波.Xilinx FPGA开发使用教程[M].北京:清华大学出版社,2009:195-198.
[13] Virtex-5 FPGA packaging and pinout specification[EB/OL].[2012-07-15] UG195 (v4.6), XILINX. May 5, 2009:16, 89.. http://www.xilinx.com/support/documentation/user_guides/ug195.pdf.
