为满足星载超高速数传设备FPGA实现的需求，充分利用FPGA器件工作处理时钟频率不高但可用并行资源丰富的特点，根据LDPC结构特性，设计一种基于FPGA的N位可配置的LDPC编码通用并行架构，它具有通用性强、传输速率高、传输延时低的特点。此外，从理论上分析并行架构与传统串行架构的等价性，并详细推导并行度N与速率及硬件资源的限制关系。最后以N=8为例，在FPGA开发平台实现吞吐量为2.5 Gbps的LDPC编码，验证架构的可行性。
In order to meet the requirements of FPGA implementation of spaceborne ultra-high speed data transmission equipment and to make full advantage of the abundant parallel resources of FPGA devices to solve the problem of low work processing clock frequency, we propose and design a general parallel architecture of LDPC coding with N-bit configurable. The architecture is designed based on FPGA according to the characteristics of LDPC structure. The equivalence between parallel architecture and traditional serial architecture is theoretically analyzed and successfully validated by simulation. Taking N=8 as an example, the LDPC code with a throughput of 2.5 Gbps is implemented on the FPGA development platform, which verifies the feasibility of the proposed architecture.
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