一种面向FPGA实现的LDPC编码可配置并行架构设计

doi:10.7523/j.issn.2095-6134.2020.05.017

中国科学院大学学报 ›› 2020, Vol. 37 ›› Issue (5): 714-719.DOI: 10.7523/j.issn.2095-6134.2020.05.017

• 简报 • 上一篇

一种面向FPGA实现的LDPC编码可配置并行架构设计

张雪, 姜泉江, 梁广, 余金培

中国科学院上海微系统与信息技术研究所, 上海 200050;上海微小卫星创新研究院, 上海 201203;上海科技大学信息科学与技术学院, 上海 201210;中国科学院大学, 北京 100049

收稿日期:2019-01-14 修回日期:2019-04-15 发布日期:2020-09-15
通讯作者: 张雪
基金资助:
国家自然科学基金（61601295）、国家重点研发计划（2017YFB0502902）和上海市启明星计划（18QA1404000）资助

Design and implementation of a generic parallel architecture for LDPC codes based on FPGA

ZHANG Xue, JIANG Quanjiang, LIANG Guang, YU Jinpei

Shanghai Institute of Microsyst&Information Technology, Chinese Academy of Science, Shanghai 200050, China;Shanghai Engineering Center for Microsatellites, Shanghai 201203, China;School of Information Science&Technology, ShanghaiTech University, Shanghai 201210, China;University of Chinese Academy of Sciences, Beijing 100049, China

Received:2019-01-14 Revised:2019-04-15 Published:2020-09-15
Supported by:

摘要/Abstract

摘要： 为满足星载超高速数传设备FPGA实现的需求，充分利用FPGA器件工作处理时钟频率不高但可用并行资源丰富的特点，根据LDPC结构特性，设计一种基于FPGA的N位可配置的LDPC编码通用并行架构，它具有通用性强、传输速率高、传输延时低的特点。此外，从理论上分析并行架构与传统串行架构的等价性，并详细推导并行度N与速率及硬件资源的限制关系。最后以N=8为例，在FPGA开发平台实现吞吐量为2.5 Gbps的LDPC编码，验证架构的可行性。

关键词: 低密度奇偶校验码, 可配置并行度, 现场可编程门阵列, 高速数传

Abstract: In order to meet the requirements of FPGA implementation of spaceborne ultra-high speed data transmission equipment and to make full advantage of the abundant parallel resources of FPGA devices to solve the problem of low work processing clock frequency, we propose and design a general parallel architecture of LDPC coding with N-bit configurable. The architecture is designed based on FPGA according to the characteristics of LDPC structure. The equivalence between parallel architecture and traditional serial architecture is theoretically analyzed and successfully validated by simulation. Taking N=8 as an example, the LDPC code with a throughput of 2.5 Gbps is implemented on the FPGA development platform, which verifies the feasibility of the proposed architecture.

Key words: LDPC, configurable parallelism, FPGA, high speed data transmission

中图分类号:

TN911.22

张雪, 姜泉江, 梁广, 余金培. 一种面向FPGA实现的LDPC编码可配置并行架构设计[J]. 中国科学院大学学报, 2020, 37(5): 714-719.

ZHANG Xue, JIANG Quanjiang, LIANG Guang, YU Jinpei. Design and implementation of a generic parallel architecture for LDPC codes based on FPGA[J]. , 2020, 37(5): 714-719.

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一种面向FPGA实现的LDPC编码可配置并行架构设计

Design and implementation of a generic parallel architecture for LDPC codes based on FPGA

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