针对传统多相位DLL（delay locked loop， DLL）电路存在的大面积、高功耗、设计周期长、不便于移植到其他工艺等缺点，提出一种产生多时钟相位输出的全数字延迟锁相环（all-digital delay locked loop，ADDLL）电路。该电路在SMIC 55nm CMOS标准工艺下基于标准单元设计实现。使用相位合成模块产生多相位输出，可以通过级联更多相位合成模块产生更多输出相位。与传统多相位DLL电路相比，ADDLL电路面积更小、功耗更低，且采用标准单元设计，可以减少设计周期。后仿真测试结果表明，该DLL能够产生21个不同相位的输出信号，工作频率范围为860MHz~1.04GHz，面积为0.0017mm2，供电电压为1.2V时功耗为2.66mW，分辨率为13ps。
The conventional multiphase DLL may suffer from the problem of large power and area, designed in a full-custom design flow that is labor intensive and cost lots of hours. An all-digital DLL is proposed to generate multiphase clock signals. The proposed DLL is designed in a cell-based design flow using SMIC 55 nm CMOS technology. In this paper, the phase-blender structure is used to generate multiphase output signals, the phase-blender structure can also be extended to multiple cascaded stages for more outputs. Compared to the traditional multiphase DLL, the proposed design is area efficient and the power consumption is low. Designed in the cell-based design flow, the paper saves a lot of hours in the design phase. Post-layout simulation results reveal that the proposed DLL operates at 860 MHz-1. 04 GHz with 21 outputs. The design occupies 0. 001 7 mm2 area and the average resolution is 13 ps. Power consumption is 2. 66 mW at the supply voltage of 1.2 V.
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