介绍了一种高性能CMOS采样/保持电路，在0.35-μm工艺、3.3-V电源和18-mW功耗下，实现了50-MHz采样频率，输入直到奈奎斯特频率仍能达到10位精度的要求。电路采用全差分结构、底极板采样、栅压自举开关技术、增益自举的折叠共源共栅跨导核心运算放大器和钳制共模电平的电平控制放大器。

A high performance CMOS sample/hold circuit is presented, which achieves the precision of 10-bit over Nyquist band in 50-MHz sampling frequency at 3.3-V supply. This circuit uses full differential circuits, bottom-plate sampling, bootstrap circuits and high performance gain-boost operational amplifier. Simulation in 0.35-μm CMOS process shows the circuit consumes 18-mW of power.