[1] Choi K, Soma R, Pedram M. Fine-grained dynamic voltage and frequency scaling for precise energy and performance trade-off based on the ratio of off-chip access to on-chip computation times //Proceedings of the Conference on Design, Automation and Test in Europe. IEEE Computer Society, 2004: 10004.
[2] Gonzalez R, Gordon B M, Horowitz M A. Supply and threshold voltage scaling for low power CMOS [J]. IEEE Journal of Solid-State Circuits, 1997, 32(8):1210-1216.
[3] Liao W, He L. Power modeling and reduction of VLIW processors //Compilers and Operating Systems for Low Power. Norwell, MA, USA:Kluwer AcademicPublishers, 2003: 155-171.
[4] AbouGhazaleh N, Mosse D, Childers B, et al. Toward the placement of power management points in real-time applications //Compilers and Operating Systems for Low Power. Norwell,MA, USA:Kluwer Academic Publishers,2003: 37-52.
[5] Moncusi M A,Arenas A, Labarta J. A modified dual-priority scheduling algorithm for hard real-time systems to improve energy savings //Compilers and Operating Systems for Low Power. Norwell,MA,USA:Kluwer Academic Publishers, 2003: 17-36.
[6] Vandecappelle A,Bougard B,Shashidhar K C,et al. Low-power design of turbo decoder with exploration of energy-throughput trade-off //Compilers and Operating Systems for Low Power. Norwell,MA,USA:Kluwer Academic Publishers,2003: 173-191.
[7] AbouGhazaleh N,Mosse D,Childers B R,et al. Collaborative operating system and compiler power management for real-time applications [J]. ACM Trans on Embedded Computing Sys, 2006, 5(1):82-115.
[8] Dick R P,Lakshminarayana G,Raghunathan A,et al. Power analysis of embedded operating systems //Proceedings of the 37th Annual Design Automation Conference. NewYork,NY,USA:ACM, 2000: 312-315.
[9] Kondo M, Nakamura H. Dynamic processor throttling for power efficient computations //Power-Aware Computer Systems, Heidel-berg:Springer,2005,3471: 120-134.
[10] Stanley-Marbell P, Hsiao M S, Kremer U. A hardware architecture for dynamic performance and energy adaptation //Power-Aware Computer Systems, Heidelberg:Springer,2003,2325: 93-96.
[11] Jayaseelan R, Mitra T. Temperature aware task sequencing and voltage scaling //Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design. Piscataway,NJ, USA:IEEE Press,2008: 618-623.
[12] Weissel A, Bellosa F. Process cruise control: event-driven clock scaling for dynamic power management //Proceedings of the 2002 International Conference on Compilers, Architecture,and Synthesis for Embedded Systems. Grenoble, France:ACM,2002: 238-246.
[13] Venkatachalam V, Franz M. Power reduction techniques for microprocessor systems [J]. ACM Comput Surv, 2005, 37(3):195-237.
[14] Simcha G, Ronny R, Ittai A, et al. The Intel Pentium M processor: microarchitecture and performance [J]. Intel Technology Journal,2003,7(2):21-36.
[15] Liao W, He L, Lepak K. Temperature and supply voltage aware performance and power modeling at microarchitecture level [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2005, 24(7):1042-1053.
[16] Intel Pentium M processor with 2-MB L2 cache and 533-MHz front side bus . 2005.
[17] Guthaus M R, Ringenberg J S, Ernst D, et al. MiBench: A free, commercially representative embedded benchmark suite //IEEE International Workshop on Workload Characterization, 2001: 3-14.
|