Realization of embedded programmable memorys word width configuration

doi:10.7523/j.issn.2095-6134.2009.4.019

›› 2009, Vol. 26 ›› Issue (4): 563-568.DOI: 10.7523/j.issn.2095-6134.2009.4.019

• Brief Report • Previous Articles Next Articles

Realization of embedded programmable memorys word width configuration

CAI Gang^1,2, YANG Hai-Gang¹

1. Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China;
2. Graduate University of the Chinese Academy of Sciences, Beijing 100049, China

Received:2008-12-30 Revised:2009-03-02 Online:2009-07-15

Abstract

Abstract:

A scheme for realization of word-width configuration in embedded programmable memories using synchronous dual-port memory IP and standard cell is proposed. The method reduces the implementing complexity and further improves the designs efficiency. The structure of embedded programmable memorys word width configuration is optimized by registering the output control signals to improve the readout datas stability. Experiment results show that the optimized structure has the advantage of implementing complex circuits with higher performance. The embedded programmable memory based on this optimized structure has been fabricated in SMIC 0.18μm 1P6M CMOS process. According to the measurement results, the fabricated embedded programmable memorys readout data has good stability and it has comparable performance in readout time with the reference to those full custom commercial embedded programmable memories based on the similar process and memory capacity.

Key words: embedded programmable memory, word width configuration, memory IP, standard cell

CLC Number:

TN402

CAI Gang, YANG Hai-Gang. Realization of embedded programmable memorys word width configuration[J]. , 2009, 26(4): 563-568.

References

[1] Lawal N, ONils M. Embedded FPGA memory requirements for real-time video processing applications //23^rd NORCHIP Conference. 2005:206-209.

[2] Yu H, Jose S, CA(US). Dual port PLD embedded memory block to support read-before-write in one clock cycle, US 7,206,251 B1 . 2007-04-17 . http://patft.uspto.Gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=7206251.PN.&OS=PN/7206251&RS=PN/7206251

[3] Yu H, Jose S, CA(US), et al. Divisible true dual port memory system supporting simple dual port memory subsystems. US 7,269,089 B1 . 2007-09-11 . http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1& f=G&l=50&co1=AND &d=PTXT&s1=7269089.PN.&OS=PN/7269089&RS=PN/7269089

[4] Lytle C S, View M, Faria D F, et al. Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory. US 6,340,897 B1 . 2002-01-22 . http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=6340897.PN.&OS=PN/6340897&RS=PN/6340897

[5] Leblance M A. Sunnyvale. memory implementations of shift registers. US 7,093,084 B1 . 2006-08-15 .http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=7093084.PN.&OS=PN/7093084&RS=PN/7093084

[6] Ratford V. Make your SOC design a winner: select the right memory IP //Proceedings of the 2002 Design, Automation and Test in Europe Conference and Exhibition.2002:15.

[7] Altera corporation. Cyclone Device Handbook , 2008, 1: 99-189 . http://www.altera. com. cn/literature/hb/cyc/cyc_c5v1.pdf

[8] Xilinx Corporation. Virtex-5 FPGA user guide . 2008 :111-170. http://www.xilinx.com /support/documentation /virtex-5.htm

[9] Ngai T, Rose J, Wilton S J E. An SRAM-programmable field-configurable memory //IEEE CustomIntegrated Circuits Conference. 1995:499-502.

Realization of embedded programmable memorys word width configuration

PDF (PC)

Knowledge

Abstract

Cite this article

share this article

References

Related Articles 0

Recommended Articles

Metrics

Comments