Implementation and optimization of high speed AES algorithm based on GPGPU and CUDA

doi:10.7523/j.issn.2095-6134.2011.6.011

›› 2011, Vol. 28 ›› Issue (6): 776-785.DOI: 10.7523/j.issn.2095-6134.2011.6.011

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Implementation and optimization of high speed AES algorithm based on GPGPU and CUDA

GU Qing¹, GAO Neng², BAO Zhen-Zhen³, XIANG Ji²

1. National 863 Program Research Center for Information Security Infrastructure, Shanghai 200336, China;
2. State Key Laboratory of Information Security, Graduate University, Chinese Academy of Sciences, Beijing 100049, China;
3. University of Science and Technology of China, Hefei 230026, China

Received:2010-07-23 Revised:2010-11-01 Online:2011-11-15

Abstract

Abstract:

Compared with the CPU which is good at handling logic complexity service, GPGPU (general purpose graphic processing unit) is suitable for large-scale parallel processing computing. The emergence of CUDA (compute unified device architecture) accelerates the expansion of application of GPGPU. We accelerate the implementation of AES algorithm based on GPGPU and CUDA and achieve a total throughput of 6~7Gbit/s. Regardless of the time of data loading and storing, a throughput of 20Gbit/s towards an input size over 1MB can be achieved.

Key words: GPGPU(general purpose graphic processing unit), CUDA(compute unified device architecture), AES algorithm, parallel computing

CLC Number:

TP393

GU Qing, GAO Neng, BAO Zhen-Zhen, XIANG Ji. Implementation and optimization of high speed AES algorithm based on GPGPU and CUDA[J]. , 2011, 28(6): 776-785.

References

[1] Kedem G,Ishihara Y. Brute force attack on UNIX passwords with SIMD computer //Proceedings of the 8th USENIX Security Symposium.1999.

[2] Olano M, Lastra A. A shading language on graphics hardware: the PixelFlow shading system
[J]. Journal of Computer Graphics,1998:159-168.

[3] Cook D L, Keroymytis A D. Cryptographics: exploiting graphics cards for security //Advancements in Information Security Series. Springer, 2006.

[4] Cook D L, Ioannidis J, Keromytis A D, et al. CryptoGraphics: secret key cryptography using graphics cards //RSA Conference, Cryptographer's Track (CT-RSA). 2005.

[5] Cook D L, Baratto R, Keromytis A. Remotely keyed cryptographics secure remote display access using (mostly) untrusted hardware //ICICS05 Conference Proceedings. December 2005.

[6] Manavski S A. CUDA compatible GPU as an efficient hardware accelerator for AES cryptography //2007 IEEE International Conference on Signal Processing and Communications (ICSPC 2007). Dubai, United Arab Emirates,November 2007.

[7] Harrison O, Waldron J. AES encryption implementation and analysis on commodity graphics processing units //Ches 2007. LNCS,2007,4727:209-226.

[8] Fiorese C, Budak C. AES on GPU: a CUDA implementation //Proc of CHES. 2007.

[9] Yamanouchi T. GPU Gems 3 . chapter 36: AES encryption and decryption on the GPU . SEGA Corporation. http://http.developer.nvidia.com/GPUGems3/gpugems3_ch36.html.

[10] Biagio A D, Barenghi A, Agosta G, et al. Design of a parallel aes for graphics hardware using the cuda framework //IEEE International Symposium on Parallel& Distributed Processing. May 2009.

[11] Joppe W Bos1, Dag Arne Osvik, Deian Stefan. Fast implementations of AES on various platforms //EPFL IC IIF LACAL, Station 14, CH-1015 Lausanne, Switzerland Fjoppe Bos, Dept of Electrical Engineering. The Cooper Union, NY 10003, New York, USA,2009.

Implementation and optimization of high speed AES algorithm based on GPGPU and CUDA

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