A novel wide-range digital duty-cycle-correction circuit with fixed rising edges

doi:10.7523/j.issn.2095-6134.2012.4.010

›› 2012, Vol. 29 ›› Issue (4): 501-506.DOI: 10.7523/j.issn.2095-6134.2012.4.010

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A novel wide-range digital duty-cycle-correction circuit with fixed rising edges

CHEN Zhu-Jia^1,2, YANG Hai-Gang¹

1. Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China;
2. Graduate University, Chinese Academy of Sciences, Beijing 100049, China

Received:2011-04-22 Revised:2011-05-11 Online:2012-07-15

Abstract

Abstract: A novel all-digital CMOS duty-cycle-correction (DCC) circuit with wide correction ranges of input duty cycle is proposed in FPGA. The proposed DCC circuit has the fixed rising edge. A successive approximation register circuit is utilized to reduce the adjusting time of the DCC. The proposed circuit is fabricated in a 0.13 μm CMOS standard technology. Measurement results show that the DCC adjusts the output duty cycle to 50%±2% for a wide input duty cycle range from 10% to 85%. The DCC could operate within a frequency range from 80 MHz to 250 MHz with the adjusting time of 6 clock cycles.

Key words: duty cycle correction, successive approximation register, duty detector

CLC Number:

TN432

CHEN Zhu-Jia, YANG Hai-Gang. A novel wide-range digital duty-cycle-correction circuit with fixed rising edges[J]. , 2012, 29(4): 501-506.

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A novel wide-range digital duty-cycle-correction circuit with fixed rising edges

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