A CMOS high performance 50MSPS sample/hold circuit

doi:10.7523/j.issn.2095-6134.2007.6.010

›› 2007, Vol. 24 ›› Issue (6): 788-793.DOI: 10.7523/j.issn.2095-6134.2007.6.010

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A CMOS high performance 50MSPS sample/hold circuit

LI Tie, GUO Li, BAI Xue-fei

Department of Electronic Science and Technology, USTC

Received:1900-01-01 Revised:1900-01-01 Online:2007-11-15

Abstract

Abstract: A high performance CMOS sample/hold circuit is presented, which achieves the precision of 10-bit over Nyquist band in 50-MHz sampling frequency at 3.3-V supply. This circuit uses full differential circuits, bottom-plate sampling, bootstrap circuits and high performance gain-boost operational amplifier. Simulation in 0.35-μm CMOS process shows the circuit consumes 18-mW of power.

Key words: sample/hold, CMOS, bootstrap, gain-boost operational amplifier

CLC Number:

TN432

LI Tie, GUO Li, BAI Xue-fei. A CMOS high performance 50MSPS sample/hold circuit[J]. , 2007, 24(6): 788-793.

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A CMOS high performance 50MSPS sample/hold circuit

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