Abstract: Test compression has drawn significant attentions of academies and industries recently, since it can reduce test data volume and test application time of integrated circuits without losing fault coverage, therefore to diminish the gap between the test and manufacture camps. Based on test stimulus and test response, the test compression techniques can be classified to two categories, that is, test stimulus compression and test response compaction. This thesis conducts the research on both fields and presents several compression methods. The contributions of the thesis include: 1. This thesis presents a Variable-Tail code, and shows how to use this code to compress the test stimulus. Variable-Tail code is a variable-length-to-variable-length code. It can achieve higher test compression ratio in the case of high X-bit density. The experimental results show that the compression ratio of Variable-Tail with the proposed reordering algorithm is close to the theoretical upper bound of predictive codes (the average distance is only about 1.26%), meanwhile up to 20% of test power is saved. 2. This thesis presents the parallel core wrapper design. Studying on the distributions of X-bit, we find the phenomenon of full overlapping and partial overlapping of scan slices. When the slices overlap continuously, they can be loaded only once, thus test application time and test power are significantly saved. The experimental results show when the parallel core wrapper design is applied, compared with the serial core wrapper design, the test application time is reduced to 2/3 and test power is reduced to 1/15. 3．The 3X compression architecture is the main contribution of this thesis. The 3X architecture consists of three parts: X-Config stimulus compression, X-Balance test generation and X-Tolerant response compaction. X-Config stimulus decompression uses a periodically alterable MUXs network. X-Balance test generation considers the dynamic compaction, compression, scan chain design and periodically alterable MUXs network as a whole. It applies two algorithms, the one is the backward patterns remove algorithm and the other one is the specified bits based scan chain design algorithm. X-Tolerant response compaction uses a single-output compactor based on convolutional code. Since only one output pin is needed, X-Tolerant response compaction guarantees the highest compaction ratio. In order to achieve the X-Tolerant capacity, a multiple-weights basic check matrix generation algorithm is presented.

Key words: System-On-a-Chip, test stimulus compression, test response compaction, scan chain design, automatic test patterns generation（ATPG）, don’t care bits, unknown bits, convolutional code