The increase of FFT computing speed is the main subject in the realm of digital signal processing. Parallel computing and pipeline structure are the basic technologies to achieve high speed of large scale FFT computing. After analyzing the address of computing data in radix-2 decimation-in-time FFT algorithm, we design a two-dimension SRAM. The non-linear changing of data address, which is the bottleneck when using normal SRAM to compute an N-point FFT, can be removed. butterfly units in FFT can compute fluently in parallel. The amount of simplified data address can be decreased largely. An 8 by 8 words, 16 bits word length, two-dimension SRAM is designed and simulated, the function is verified.