Journal of University of Chinese Academy of Sciences >
A low-noise and low-offset capacitive readout circuit
Received date: 2009-04-13
Revised date: 2009-05-04
Online published: 2009-11-15
This paper presents a novel structure of capacitive readout circuit for fully differential capacitive sensor. The operation of this circuit is controlled by a nonoverlapping two-phase clock. This circuit is not sensitive to parasitic capacitor. Using correlated double sampling(CDS), the low-frequency noise and voltage offset have been suppressed, so that the resolution and dynamic range of the circuit have been improved. The experiment chip has been fabricated in the standard 0.35μm CMOS process, with a single 5V power supply, and the die size is 0.7mm×1.8mm. The results show that the readout circuit achieves a resolution of 0.4aF/√Hz with 118dB dynamic range under 1MHz sampling frequency.
Key words： capacitive sensor; capacitive readout circuit; CDS
WU Qi-Song , YANG Hai-Gang , ZHANG Chong , Yin Tao . A low-noise and low-offset capacitive readout circuit[J]. Journal of University of Chinese Academy of Sciences, 2009 , 26(6) : 789 -794 . DOI: 10.7523/j.issn.2095-6134.2009.6.009
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