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A Σ-Δ fractional-N frequency synthesizer with low in-band phase noise
Received date: 2009-12-09
Revised date: 2010-05-11
Online published: 2010-11-15
In order to achieve low in-band phase noise in Σ-Δ fractional-N frequency synthesizers, a 5th-order 4bit Σ-Δ modulator is used to replace a 3rd-order MASH modulator. A 2.6GHz Σ-Δ fractional-N frequency synthesizer with low in-band phase noise and fast-locking characteristics was implemented in 0.25μm CMOS process. The measurement results show that the in-band phase noise of this synthesizer is -86.5dBc/Hz (at 40KHz offset), and all the spurs are less than - 65dBc. The whole synthesizer excluding the Σ-Δ modulator consumes 25.5mA in the case of 2.5V supply, and it occupies 3.9mm2(with a core area of 0.63mm2).
Key words： Σ-Δ modulator; frequency synthesizer; MASH; CMOS; PLL
YU Yun-Feng , YE Tian-Chun , MA Cheng-Yan , YUE Jian-Lian , GAN Ye-Bing . A Σ-Δ fractional-N frequency synthesizer with low in-band phase noise[J]. Journal of University of Chinese Academy of Sciences, 2010 , 27(6) : 782 -787 . DOI: 10.7523/j.issn.2095-6134.2010.6.008
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