Journal of University of Chinese Academy of Sciences >
Design of CCSDS image compression system based on FPGA
Received date: 2010-04-15
Revised date: 2010-05-12
Online published: 2011-01-20
We report the design and implementation of CCSDS image data compression (IDC) parallel scheme based on FPGA. This scheme includes four modules: discrete wavelet transform(DWT), direct coefficient quantified encoding, bit plane encoding(BPE),and code processing. In order to put on speed, we use the parallel scanning and parallel encoding in the BPE module. The experimental results show the feasibility and efficiency of this scheme, and compared to the modified method of CCSDS IDC serial encoding, the processing time has reduced by 13.6%. Our scheme is fit for image data compression in the space communication.
Key words： CCSDS; image compression; bit plane encoding; FPGA
CHEN Zhe , TU Guo-Fang , ZHANG Can , CHEN De-Yuan . Design of CCSDS image compression system based on FPGA[J]. Journal of University of Chinese Academy of Sciences, 2011 , 28(1) : 101 -107 . DOI: 10.7523/j.issn.2095-6134.2011.1.015
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