Welcome to Journal of University of Chinese Academy of Sciences,Today is

Architecture design and optimization for motion estimation with dynamic search range

  • CHEN Yun-Bi ,
  • GUO Li ,
  • LI Zheng-Dong ,
  • CHI Ling-Hong
Expand
  • 1. Department of Electronic Science and Technology, University of Science and Technology of China, Hefei 230027, China;
    2. Staff room of Electronic and Technology, Chongqing Communication College, Chongqing 400035, China

Received date: 2011-03-14

  Revised date: 2011-06-07

  Online published: 2012-07-15

Abstract

A VBSME with dynamic search range is proposed to overcome the defects of the engine with fixed search range, and it reduces off-chip bandwidth, computational complexity, and power dissipation. A circularly distributed storage structure is adopted to realize the access to the dynamic search area. Besides, the time-consuming SAD computing array is divided into the balanced and adder-optimized pipelines. The implementation results show that, compared to traditional engines, the proposed engine can achieve significant improvements of the hardware and the power efficiency without much loss of throughput.

Cite this article

CHEN Yun-Bi , GUO Li , LI Zheng-Dong , CHI Ling-Hong . Architecture design and optimization for motion estimation with dynamic search range[J]. Journal of University of Chinese Academy of Sciences, 2012 , 29(4) : 512 -517 . DOI: 10.7523/j.issn.2095-6134.2012.4.012

References

[1] Wiegand T, Sullivan G J, Bjontegaard G, et al. Overview of the H.264/AVC video coding standard[J]. IEEE Trans Circuits Syst Video Technol, 2003, 13(7):560-576.
[2] Wiegand T, Schwarz H, Joch A, et al. Rate-constrained coder control and comparison of video coding standards[J]. IEEE Trans Circuits Syst Video Technol, 2003, 13(7):688-703.
[3] Huang Y W, Hsieh B Y, Chien S Y, et al. Analysis and complexity reduction of multiple reference frames motion estimation in H.264/AVC[J]. IEEE Trans Circuits Syst Video Technol, 2006, 16(4):507-522.
[4] Deng L, Gao W, Hu M Z, et al. An efficient hardware implementation for motion estimation of AVC standard[J]. IEEE Trans Consum Electron, 2005, 51(4):1360-1366.
[5] Li D X, Zheng W, Zhang M. Architecture design for H.264/AVC integer motion estimation with minimum memory bandwidth[J]. IEEE Trans Consum Electron, 2007, 53(3):1053-1060.
[6] Cao W, Hou H, Tong J R, et al. A high-performance reconfigurable VLSI architecture for VBSME in H.264[J]. IEEE Trans Consum Electron, 2008, 54(3):1338-1345.
[7] Ou C M, Le C F, Hwang W J. An efficient VLSI architecture for H.264 variable block size motion estimation[J]. IEEE Trans Consum Electron, 2005, 51(4):1291-1299.
[8] Jung J, Kim J, Kyung C M. A dynamic search range algorithm for stabilized reduction of memory traffic in video encoder[J]. IEEE Trans Circuits Syst Video Technol, 2010, 20(7):1041-1046.
[9] Zhang L, Xie D, Wu D. Improved FFSBM algorithm and its VLSI architecture for AVS video standard[J]. Journal of Computer Science and Technology, 2006, 21(3):378-382.
[10] Tuan J C, Chang T S, Jen C W. On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture[J]. IEEE Trans Circuits Syst Video Technol, 2002, 12(1):61-72.
[11] Chen Z X, Song Y, Ikenaga T, et al. A dynamic search range algorithm for variable block size motion estimation in H.264/AVC //Proceedings of the 6th International Conference on Information, Communications & Signal Processing. Singapore: IEEE Communications Society, 2007:1-4.
[12] Chen T C, Chien S Y, Huang Y W, et al. Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder[J]. IEEE Trans Circuits Syst Video Technol, 2006, 16(6): 673-688.
[13] Chen Y B, Guo L, Li Z D, et al. An efficient parallel architecture for one-bit transform based motion estimation[J]. Journal of Electronics & Information Technology, 2011, 33(3): 717-722(in Chinese). 陈运必, 郭立, 李正东, 等. 高性能并行比特变换运动估计硬件架构设计[J]. 电子与信息学报, 2011, 33(3):717-722.
Outlines

/