Journal of University of Chinese Academy of Sciences >
A group management to balance power, performance, and fairness
Received date: 2012-06-06
Revised date: 2012-11-12
Online published: 2013-07-15
We present a group management to balance power, performance, and fairness. This management partitions all threads into different groups based on each thread's power behavior characteristic, combines dynamic voltage and frequency scaling and dynamic power scaling which are provided by architecture and scheduler of the operating system, and realizes threadgroup-based management (TGM). TGM optimizes system power under tight system performance and fairness among thread constraints. Experimental results show that TGM reduces power by 16.7% on average with tightly guaranteed system performance and neglected overhead in fairness.
Key words： power; performance; fairness; threadgroup-based management; scheduler
JIA Gang-Yong , LI Xi , ZHOU Xue-Hai , ZHU Zong-Wei . A group management to balance power, performance, and fairness[J]. Journal of University of Chinese Academy of Sciences, 2013 , 30(4) : 555 -561 . DOI: 10.7523/j.issn.2095-6134.2013.04.018
[1] Choi K, Soma R, Pedram M. Fine-grained dynamic voltage and frequency scaling for precise energy and performance trade-off based on the ratio of off-chip access to on-chip computation times[C]//Proceedings of the Conference on Design, Automation and Test in Europe. IEEE Computer Society, 2004: 10004.
[2] Ayoub R, Rosing T. Cool and save: cooling aware dynamic workload scheduling in multi-socket cpu systems[C]//ASP-DAC, 2010: 891-896.
[3] Shin D, Kim J, Lee S. Low-energy intra-task voltage scheduling using static timing analysis[C]//DAC. 2001: 438-443.
[4] Cai Q, Jos G, Ryan R, et al. Meeting Points: using thread criticality to adapt multicore hardware to parallel regions[C]//PACT'08: Proceedings of the 17th international conference on Parallel architectures and compilation techniques. New York, NY, USA, 2008: 240-249.
[5] Liu C, Anand S, Mahmut K, et al. Exploiting Barriers to Optimize Power Consumption of CMPs[C]//IEEE international Parallel and Distributed Processing Symposium. 2005.
[6] Dhiman G, Rosing T S. Dynamic voltage frequency scaling for multi-task systems using online learning[C]//2007 International Symposium on Low Power Electronics and Design. New York, 2007.
[7] Mao Y L, Chen X L, Tang L, et al. Best energy-saving frequency in time-sharing system and its realization[J]. Journal of the Graduate School of the Chinese Academy of Sciences, 2010, 27(3): 404-413(in Chinese). 毛熠璐,陈香兰,唐玲,等. 分时系统最佳节能频率及其实现方法[J]. 中国科学院研究生院学报,2010,27(3): 404-413.
[8] Kolpe T, Zhai A, Sapatnekar, et al. Enabling improved power management in multicore processors through clustered DVFS[C]//Proc of Design, Automation & Test in Europe Conference & Exhibition. 2011.
[9] Venkatachalam V, Franz M. Power reduction techniques for microprocessor systems[J]. ACM Comput Surv, 2005, 37(3):195-237.
[10] Choi K, Soma R, Pedram M. Dynamic voltage and frequency scaling based on workload decomposition[C]//ISLPED. 2004: 174-179.
[11] Herbert S, Marculescu D. Analysis of dynamic voltage/frequency scaling in chip-multiprocessors[C]//ISLPED. 2007: 38-43.
[12] Cai Q, Gonzalez J, Magklis G, et al. Thread shuffling: Combining DVFS and thread migration to reduce energy consumptions for multi-core systems[C]//2011 International Symposium on Low Power Electronics and Design. Aug. 2011.
[13] Chandandeep S P. Completely fair scheduler [CP]. Linux Journal archive, 2009:2009(184).
[14] SPEC: standard performance evaluation corporation [S/OL]. [2012-05-12]. http://www.spec.org/cpu2000/.
[15] Guthaus M R, Ringenberg J S, Ernst D, et al. MiBench: A free, commercially representative embedded benchmark suite[C]//IEEE International Workshop on Workload Characterization. 2001: 3-14.
[16] Kopytov A. SysBench: a system performance benchmark [EB/OL]. [2012-05-12]. http://sysbench.sourceforge.net/index.html. 2004.
/
| 〈 |
|
〉 |