In order to meet the requirements of FPGA implementation of spaceborne ultra-high speed data transmission equipment and to make full advantage of the abundant parallel resources of FPGA devices to solve the problem of low work processing clock frequency, we propose and design a general parallel architecture of LDPC coding with N-bit configurable. The architecture is designed based on FPGA according to the characteristics of LDPC structure. The equivalence between parallel architecture and traditional serial architecture is theoretically analyzed and successfully validated by simulation. Taking N=8 as an example, the LDPC code with a throughput of 2.5 Gbps is implemented on the FPGA development platform, which verifies the feasibility of the proposed architecture.
ZHANG Xue
,
JIANG Quanjiang
,
LIANG Guang
,
YU Jinpei
. Design and implementation of a generic parallel architecture for LDPC codes based on FPGA[J]. Journal of University of Chinese Academy of Sciences, 2020
, 37(5)
: 714
-719
.
DOI: 10.7523/j.issn.2095-6134.2020.05.017
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