This paper proposes a clock tree design method that meets timing as much as possible and minimizes power consumption. This method uses fanout number and driver selection strategy as the optimization variables for low-power clock tree design. For different fanout numbers, we take the driver selection strategy of selecting all inverters/buffers in the standard cell library as the reference strategy,and comparing and analyzing the three driver selection strategies with partial inverters/buffers proposed in this article. At the same time, the merit factor composed of the clock skew and power consumption of the clock tree is proposed as the criterion for evaluating various driver selection strategies. The experimental results show that with the merit factor as the evaluation criterion, the optimal fanout number in the clock tree design has little correlation with the driver selection strategy, and the three driver selection strategies proposed in this paper are better than the reference strategy. In the strategy with the best merit factor, the power consumption of the clock tree is reduced by 5.82% typically. Finally, this paper presents a low power clock tree design method based on merit factor.
ZHU Jiaqi
,
CHEN Lan
,
WANG Haiyong
. Low power clock tree[J]. Journal of University of Chinese Academy of Sciences, 2023
, 40(2)
: 203
-207
.
DOI: 10.7523/j.ucas.2021.0040
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