一种新型宽范围固定上升沿的数字占空比矫正电路

doi:10.7523/j.issn.2095-6134.2012.4.010

中国科学院大学学报 ›› 2012, Vol. 29 ›› Issue (4): 501-506.DOI: 10.7523/j.issn.2095-6134.2012.4.010

一种新型宽范围固定上升沿的数字占空比矫正电路

陈柱佳^1,2, 杨海钢¹

1. 中国科学院电子学研究所可编程芯片与系统研究室, 北京 100190;
2. 中国科学院研究生院, 北京 100049

收稿日期:2011-04-22 修回日期:2011-05-11 发布日期:2012-07-15
通讯作者: 杨海钢
基金资助:
国家高技术研究发展计划(863)(2008AA010701)资助

A novel wide-range digital duty-cycle-correction circuit with fixed rising edges

CHEN Zhu-Jia^1,2, YANG Hai-Gang¹

1. Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China;
2. Graduate University, Chinese Academy of Sciences, Beijing 100049, China

Received:2011-04-22 Revised:2011-05-11 Published:2012-07-15

摘要/Abstract

摘要： 提出一种应用于FPGA中的新型宽调整范围的数字占空比矫正电路. 该电路在0.13 μm CMOS标准工艺下实现,具有固定上升延时的特性. 通过采用连续逼近寄存器,实现了占空比的快速调整. 测试结果表明,其调整范围为10%~85%,在80~250 MHz输入范围内输出占空比变化为50％±2％,所需调整时间为6个时钟周期.

关键词: 占空比矫正, 连续逼近寄存器, 占空比检测

Abstract: A novel all-digital CMOS duty-cycle-correction (DCC) circuit with wide correction ranges of input duty cycle is proposed in FPGA. The proposed DCC circuit has the fixed rising edge. A successive approximation register circuit is utilized to reduce the adjusting time of the DCC. The proposed circuit is fabricated in a 0.13 μm CMOS standard technology. Measurement results show that the DCC adjusts the output duty cycle to 50%±2% for a wide input duty cycle range from 10% to 85%. The DCC could operate within a frequency range from 80 MHz to 250 MHz with the adjusting time of 6 clock cycles.

Key words: duty cycle correction, successive approximation register, duty detector

中图分类号:

TN432

陈柱佳, 杨海钢. 一种新型宽范围固定上升沿的数字占空比矫正电路[J]. 中国科学院大学学报, 2012, 29(4): 501-506.

CHEN Zhu-Jia, YANG Hai-Gang. A novel wide-range digital duty-cycle-correction circuit with fixed rising edges[J]. , 2012, 29(4): 501-506.

参考文献

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一种新型宽范围固定上升沿的数字占空比矫正电路

A novel wide-range digital duty-cycle-correction circuit with fixed rising edges

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