欢迎访问中国科学院大学学报,今天是

中国科学院大学学报 ›› 2010, Vol. 27 ›› Issue (5): 690-694.DOI: 10.7523/j.issn.2095-6134.2010.5.017

• 论文 • 上一篇    下一篇

数字PID控制器的硬件优化设计

蔡晓宁1,2, 陈仲林1, 董戈1, 谢珊英1,2   

  1. 1. 中国科学院电子学研究所,北京 100190;
    2. 中国科学院研究生院,北京 100049
  • 收稿日期:2010-03-31 修回日期:2010-04-16 发布日期:2010-09-15
  • 通讯作者: 蔡晓宁
  • 基金资助:

    国家高技术研究发展计划(863)项目(2007AA12Z123)资助 

Optimization of digital PID controller on hardware

CAI Xiao-Ning1,2, CHEN Zhong-Lin1, DONG Ge1, XIE Shan-Ying1,2   

  1. 1 Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China; 2 Graduate University of the Chinese Academy of Sciences, Beijing 100049, China
  • Received:2010-03-31 Revised:2010-04-16 Published:2010-09-15

摘要:

研究了PID控制器的数字电路实现方法. 通过对数字PID算法进行流水线设计,提高了算法运行效率;通过对加法器和乘法器采用有符号二进制小数操作,减小了电路面积. 该算法在Actel AFS600芯片上实现,仿真结果表明了该方案的可行性和有效性.

关键词: 数字PID控制器, FPGA, AFS600, 流水线, SBF

Abstract:

PID control method is widely used in the feed-back circuit of switch mode power supply. Since the analog PID controller is sensitive to temperature and electromagnetic interference, we discuss hardware implementation of digital PID controller in the present paper. With pipeline operation the efficiency of the algorithm was improved, and with signed binary fraction operation the resource cost of the circuit was reduced. Finally, this digital PID algorithm was implemented on an Actel AFS600 FPGA chip, and simulation result shows its efficiency and feasibility.

Key words: digital PID controller, FPGA, AFS600, pipeline, SBF

中图分类号: