Interpolation-based anti-jamming E-D-gate DS-SS code tracking architecture

doi:10.7523/j.issn.2095-6134.2009.4.012

Abstract

Abstract:

DS-SS is widely used in LEO satellite communication. Since jamming exists in UHF/VHF wave band, which is commonly selected by LEO communication system, anti-jamming module is necessary in receivers. To control the power consuming, an interpolation-based one-sample-per-chip receiver architecture is developed. Performance analyses show that this architecture cuts off half of anti-jamming module computation burden at the cost of the SNR lose less than 0.1dB. By this approach, computation burden and power consuming can be reduced remarkably.

Key words: interpolation, E-D-gate, anti-jamming, low-power-consuming

CLC Number:

TN91

TIAN Yu, LI Guo-Tong, YANG Gen-Qing. Interpolation-based anti-jamming E-D-gate DS-SS code tracking architecture[J]. , 2009, 26(4): 513-516.

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Interpolation-based anti-jamming E-D-gate DS-SS code tracking architecture

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