[1] Jerraya A, Wolf W. Multiprocessor systems-on-chips[M]. San Francisco, USA: Morgan Kaufmann Publishers, 2004.
[2] Pericas M, Cristal A, Cazorla F J, et al. A flexible heterogeneous multi-core architecture //16th International Conference on Parallel Architecture and Compilation Techniques(PACT 2007). 2007:13-24.
[3] Vassiliadis S, Wong S, Gaydadjiev G, et al. The MOLEN polymorphic processor[J]. IEEE Transactions on Computers, 2004, 53(11): 1363-1375.
[4] Givargis T, Vahid F. Platune: a tuning framework for system-on-a-chip platforms[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002, 21(11): 1317-1327.
[5] Wawrzynek J, Patterson D, Oskin M, et al. RAMP: research accelerator for multiple processors[J]. Micro IEEE, 2007, 27(2): 46-57.
[6] Silvano C. Multicube: multi-objective design space exploration of multi-processor SoC architectures for embedded multimedia applications. Politecnico di Milano, 2008.
[7] Ahmadinia A, Arslan T, Canque H F. Optimization of reconfigurable multi-core SOCs for multi-standard applications //Proceedings of the 13th International Conference on Knowledge-Based and Intelligent Information and Engineering Systems: Part II. Berlin, Germany: Springer-Verlag, 2009: 515-522.
[8] Dittmann F, Gotz M, Rettberg A. Model and Methodology for the Synthesis of Heterogeneous and Partially Reconfigurable Systems //IEEE International Parallel and Distributed Processing Symposium. 2007:1-8.
[9] Tuan V M, Amano H. A mapping method for multi-process execution on dynamically reconfigurable processors //International Conference on Field-Programmable Technology. 2007:357-360.
[10] Tuan V M, Katsura N, Matsutani H, et al. Evaluation of a multicore reconfigurable architecture with variable core sizes //IEEE International Symposium on Parallel & Distributed Processing. 2009:1-8.
[11] Madsen J, Stidsen T K, Kjaerulf P, et al. Multi-objective design space exploration of embedded system platforms[J]. IFIP International Federation for Information Processing, 2006: 185-194.
[12] Wu M Y, Gajski D D. Hypertool: a programming aid for message-passing systems[J]. IEEE Trans on Parallel and Distributed Systems, 1990, 1(7): 330-343.
[13] Park G L, Shirazi B, Marquis J, et al. Decisive path scheduling: a new list scheduling method //Proc of International Conference on Parallel Processing. Bloomington, IL, USA: IEEE Computer Society, 1997: 534-541.
[14] Youness H, Hassan M, Sakanushi K, et al. A high performance algorithm for scheduling and hardware-software partitioning on MPSoCs //Proc of International Conference on Design and Technology of Integrated Systems in Nanoscale Era. Cairo, Egypt: IEEE Computer Society, 2009:71-76.
[15] Ma H X, Zhou X H, Gao Y Y, et al. A hardware/software task partitioning and scheduling algorithm on multi-core system on chip with reconfigurable hardware[J]. Journal of the Graduate School of the Chinese Academy of Sciences, 2010, 27(5): 664-669(in Chinese). 马宏星,周学海,高妍妍,等.一种集成可重构硬件的多核片上系统的软硬件任务划分与调度算法[J].中国科学院研究生院学报,2010, 27(5):664-669. |