Journal of University of Chinese Academy of Sciences ›› 2008, Vol. 25 ›› Issue (1): 123-128.DOI: 10.7523/j.issn.2095-6134.2008.1.017
Previous Articles Next Articles
Wang Run-ze, Wang Ying, Yang Dong-yi
Received:
Revised:
Online:
Abstract: The increase of FFT computing speed is the main subject in the realm of digital signal processing. Parallel computing and pipeline structure are the basic technologies to achieve high speed of large scale FFT computing. After analyzing the address of computing data in radix-2 decimation-in-time FFT algorithm, we design a two-dimension SRAM. The non-linear changing of data address, which is the bottleneck when using normal SRAM to compute an N-point FFT, can be removed. butterfly units in FFT can compute fluently in parallel. The amount of simplified data address can be decreased largely. An 8 by 8 words, 16 bits word length, two-dimension SRAM is designed and simulated, the function is verified.
CLC Number:
TN402
Wang Run-ze, Wang Ying, Yang Dong-yi. The Design of a Two-dimension SRAM for Parallel Computing of Large Scale FFT[J]. Journal of University of Chinese Academy of Sciences, 2008, 25(1): 123-128.
0 / / Recommend
Add to citation manager EndNote|Ris|BibTeX
URL: http://journal.ucas.ac.cn/EN/10.7523/j.issn.2095-6134.2008.1.017
http://journal.ucas.ac.cn/EN/Y2008/V25/I1/123
