A Σ-Δ fractional-N frequency synthesizer with low in-band phase noise

doi:10.7523/j.issn.2095-6134.2010.6.008

Abstract

Abstract:

In order to achieve low in-band phase noise in Σ-Δ fractional-N frequency synthesizers, a 5th-order 4bit Σ-Δ modulator is used to replace a 3rd-order MASH modulator. A 2.6GHz Σ-Δ fractional-N frequency synthesizer with low in-band phase noise and fast-locking characteristics was implemented in 0.25μm CMOS process. The measurement results show that the in-band phase noise of this synthesizer is -86.5dBc/Hz (at 40KHz offset), and all the spurs are less than - 65dBc. The whole synthesizer excluding the Σ-Δ modulator consumes 25.5mA in the case of 2.5V supply, and it occupies 3.9mm²(with a core area of 0.63mm²).

Key words: Σ-Δ modulator, frequency synthesizer, MASH, CMOS, PLL

CLC Number:

TN742.2

YU Yun-Feng, YE Tian-Chun, MA Cheng-Yan, YUE Jian-Lian, GAN Ye-Bing. A Σ-Δ fractional-N frequency synthesizer with low in-band phase noise[J]. , 2010, 27(6): 782-787.

References

[1] Lin T H, Ti C L, Liu Y H. Dynamic current-matching charge pump and gated-offset linearization technique for delta-sigma fractional-N PLLs
[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2009, 56(5):877- 885.

[2] Khalil W, Hedayati H, Bakkaloglu B, et al. Analysis and modeling of noise folding and spurious emission in wideband fractional -N synthesizers //IEEE Radio Frequency Integrated Circuits Symposium. Atlanta:MTT, 2008:291-294.

[3] Rhee W, Song B, Ali A. A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order ΔΣ modulator
[J]. IEEE Journal of Solid-State Circuits, 2000, 35 (10):1453-1460.

[4] Yang X, Chen G C, Cheng J, et al. A novel cascade ΣΔ modulator architecture
[J]. Journal of Xi’an Jiaotong University, 2008, 42(12): 1541-1545(in Chinese). 杨骁,陈贵灿,程军,等.一种新型级联ΣΔ调制器系统结构
[J]. 西安交通大学学报, 2008, 42(12):1541-1545.

[5] Aroha H, Klemmer N. Phase-noise driven system design of fractional-N frequency synthesizers and validation with measured results //IEEE Computer Society Annual Symposium on VLSI, Porto Alegre:CS, 2007:133-138.

[6] Stelbout T. Delta-sigma modulation in radio transmitter architectures // Emerging Technologies Symposium -Wireless Communications and Systems, Richardson: COM, 1999:6.1- 6.4.

[7] Jiang R X, Fiez T. A 14-bit delta-sigma ADC with 8×OSR and 4-MHz conversion bandwidth in a 0.18 μm CMOS process
[J]. IEEE Journal of Solid-State Circuits, 2004, 39(1): 63-75.

[8] Yang X, Chen G C, Cheng J, et al. A novel architecture of high-order two-channel time-interleaved ΣΔ modubtor
[J]. Journal of Xi’an Jiaotong University, 2008, 42(8): 996-1000(in Chinese). 杨骁,陈贵灿,程军,等.一种新型高阶两通道时间交织ΣΔ调制器系统结构
[J].西安交通大学学报, 2008, 42(8):996-1000.

[9] Rofougaran A, Rael J, Rofougaran M, et al. A 900 MHz CMOS LC-oscillator with quadrature outputs //IEEE International Solid-State Circuits Conference, San Francisco: SSC, 1996:392-393.

[10] Andreani P. A low-phase-noise low-phase-error 1.8GHz quadrature CMOS VCO //IEEE International Solid-State Circuits Conference, San Francisco:SSC, 2002(2):228-229.

[11] Shinmyo A, Hashimoto M, Onodera H. Design and optimization of CMOS current mode logic dividers //IEEE Asia-Pacific Conference on Advanced System Integrated Circuits. Fukuoka:SSC, 2004:434- 435.

[12] Vaucher C, Ferencic I, Locher M, et al. A family of low-power truly modular programmable dividers in standard 0.35-μm CMOS technology
[J]. IEEE Journal of Solid-State Circuits, 2000, 35(7):1039-1045.

[13] Craninckx J, Steyaert M. A fully integrated CMOS DCS-1800 frequency synthesizer
[J]. IEEE Journal of Solid-State Circuits, 1998, 33(12):2054-2065.

[14] Chang R, Kuo L C. A new low-voltage charge pump circuit for PLL //IEEE International Symposium on Circuits and Systems. Geneva:CSS, 2000(V):701-704.

[15] Ahola R, Halonen K. A 1.76-GHz 22.6-mW ΔΣ fractional-n frequency synthesizer
[J]. IEEE Journal of Solid-State Circuits, 2003, 38(1):138-140.

[16] Wang W T, Howard C. Luong. A 0.8-V 4.9-mW 1.2-GHz CMOS fractional-N frequency synthesizer for UHF RFID readers
[J]. IEEE Trans. Circuits Syst. I, Reg Papers, 2009, 55(9):2505-2513.

[17] Zhang H J, Hu K M, Hong Z L. A Σ-Δ fractional-N PLL frequency synthesizer with AFC for SRD applications
[J]. Journal of Semiconductors, 2008, 29(7):1298-1304.