An all-digital multiphase delay-locked loop with phase-blender structure

doi:10.7523/j.ucas.2020.0010

Abstract

Abstract: The conventional multiphase DLL may suffer from the problem of large power and area, designed in a full-custom design flow that is labor intensive and cost lots of hours. An all-digital DLL is proposed to generate multiphase clock signals. The proposed DLL is designed in a cell-based design flow using SMIC 55 nm CMOS technology. In this paper, the phase-blender structure is used to generate multiphase output signals, the phase-blender structure can also be extended to multiple cascaded stages for more outputs. Compared to the traditional multiphase DLL, the proposed design is area efficient and the power consumption is low. Designed in the cell-based design flow, the paper saves a lot of hours in the design phase. Post-layout simulation results reveal that the proposed DLL operates at 860 MHz-1. 04 GHz with 21 outputs. The design occupies 0. 001 7 mm² area and the average resolution is 13 ps. Power consumption is 2. 66 mW at the supply voltage of 1.2 V.

Key words: ADDLL, phase-blender, cell-based flow, area efficient, low power

CLC Number:

TN47

SUN Haoxin, HONG Qinzhi, GUAN Wu, LIANG Liping. An all-digital multiphase delay-locked loop with phase-blender structure[J]. Journal of University of Chinese Academy of Sciences, 2022, 39(2): 283-288.

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