Design and implementation of fuzzy extractor for PUF

doi:10.7523/j.ucas.2022.054

Abstract

Abstract: The physical unclonable function (PUF) implemented on SRAM and other schemes exists inherent demerit of poor reproducibility for environmental factors such as voltage changes and thermal noise. This disadvantage greatly restricts functional application in cryptography, communication and other fields. In this paper, a fuzzy extractor with large error correction capacity is designed to reconstruct the original data of SRAM by means of BCH codes (Bose-Chaudhuri-Hocquenghem Codes). The SRAM PUF chip applying this design is manufactured on the Hua Hong Grace 0.11 μm CMOS platform with area of 306 267 μm². The original BCH code has a code length of 127 bits and an error correction capability of 27 bits, which achieves the practical requirements of PUF applications.

Key words: physically unclonable function, BCH code, fuzzy extractor, digital IC design

CLC Number:

TN492

SONG Minte, HOU Kai, RU Zhanqiang, WANG Zhengguang, SONG Helun. Design and implementation of fuzzy extractor for PUF[J]. Journal of University of Chinese Academy of Sciences, 2024, 41(1): 127-135.

References

[1] Satpathy S, Mathew S, Li J T, et al. 13fJ/bit probing-resilient 250K PUF array with soft darkbit masking for 1.94% bit-error in 22 nm tri-gate CMOS[C]//ESSCIRC 2014-40th European Solid State Circuits Conference (ESSCIRC). September 22-26, 2014, Venice Lido, Italy. IEEE, 2014: 239-242. DOI:10.1109/ESSCIRC.2014.6942066.
[2] Su Y, Holleman J, Otis B. A 1.6pJ/bit 96% stable chip-ID generating circuit using process variations[C]//2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. February 11-15, 2007, San Francisco, CA, USA. IEEE, 2007: 406-611. DOI:10.1109/ISSCC.2007.373466.
[3] Lin L, Srivathsa S, Krishnappa D K, et al. Design and validation of arbiter-based PUFs for sub-45-nm low-power security applications[J]. IEEE Transactions on Information Forensics and Security, 2012, 7(4): 1394-1403. DOI:10.1109/TIFS.2012.2195174.
[4] Lin L, Holcomb D, Krishnappa D K, et al. Low-power sub-threshold design of secure physical unclonable functions[C]//2010 ACM/IEEE International Symposium on Low-Power Electronics and Design. August 18-20, 2010, Austin, TX, USA. IEEE, 2010: 43-48. DOI:10.1145/1840845.1840855.
[5] Maes R, Verbauwhede I. Physically unclonable functions: a study on the state of the art and future research directions[M]//Towards hardware-intrinsic security. Springer, Berlin, Heidelberg, 2010: 3-37. DOI:10.1007/978-3-642-14452-3_1.
[6] Suh G E, Devadas S. Physical unclonable functions for device authentication and secret key generation[C]//2007 44th ACM/IEEE Design Automation Conference. June 4-8, 2007. San Diego, CA, USA. IEEE, 2007: 9-14. DOI:10.1109/dac.2007.375043.
[7] Guajardo J, Kumar S S, Schrijen G J, et al. FPGA intrinsic PUFs and their use for IP protection[C]//Cryptographic Hardware and Embedded Systems-CHES 2007, 2007: 63-80. DOI:10.1007/978-3-540-74735-2_5.
[8] Alheyasat A, Torrens G, Bota S, et al. Bit-cell selection analysis for embedded SRAM-based PUF [C]//2020 IEEE International Symposium on Circuits and Systems. October 12-14, 2020, Seville, Spain. IEEE, 2020: 1-4. DOI: 10.1109/ISCAS45731.2020.9180780.
[9] Kim J S, Patel M, Hassan H, et al. The DRAM latency PUF: quickly evaluating physical unclonable functions by exploiting the latency-reliability tradeoff in modern commodity DRAM devices[C]//2018 IEEE International Symposium on High Performance Computer Architecture. February 24-28, 2018, Vienna, Austria. IEEE, 2018: 194-207. DOI:10.1109/HPCA.2018.00026.
[10] Ni L, Wang P J, Zhang Y J, et al. A reliable multi-information entropy glitch PUF using schmitt trigger sampling method for IoT security[C]//2021 IEEE 14th International Conference on ASIC. October 26-29, 2021, Kunming, China. IEEE, 2021: 1-4. DOI:10.1109/ASICON52560.2021.9620406.
[11] Shifman Y, Miller A, Weizman Y, et al. An SRAM PUF with 2 independent bits/cell in 65 nm[C]//2019 IEEE International Symposium on Circuits and Systems. May 26-29, 2019, Sapporo, Japan. IEEE, 2019: 1-5. DOI:10.1109/ISCAS.2019.8702612.
[12] Pang Y C, Wu H Q, Gao B, et al. A novel PUF against machine learning attack: implementation on a 16 Mb RRAM chip[C]//2017 IEEE International Electron Devices Meeting. December 2-6, 2017, San Francisco, CA, USA. IEEE, 2017: 12.2.1-12.2.4. DOI:10.1109/IEDM.2017.8268376.
[13] Satpathy S, Mathew S K, Suresh V, et al. A 4-fJ/b delay-hardened physically unclonable function circuit with selective bit destabilization in 14-nm trigate CMOS[J]. IEEE Journal of Solid-State Circuits, 2017, 52(4): 940-949. DOI:10.1109/JSSC.2016.2636859.
[14] Dodis Y, Reyzin L, Smith A. Fuzzy extractors: how to generate strong keys from biometrics and other noisy data[M]//Advances in Cryptology-EUROCRYPT 2004. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004: 523-540. DOI:10.1007/978-3-540-24676-3_31.
[15] Tuyls P, Akkermans A H M, Kevenaar T A M, et al. Practical biometric authentication with template protection[C]//Audio- and Video-Based Biometric Person Authentication, 2005: 436-446. DOI:10.1007/11527923_45.
[16] Hao F, Anderson R, Daugman J. Combining crypto with biometrics effectively[J]. IEEE Transactions on Computers, 2006, 55(9): 1081-1088. DOI:10.1109/TC.2006.138.
[17] van der Veen M, Kevenaar T, Schrijen G J, et al. Face biometrics with renewable templates[C]//Proc SPIE 6072, Security, Steganography, and Watermarking of Multimedia Contents VIII, 2006, 6072: 205-216. DOI:10.1117/12.643176.
[18] Bösch C, Guajardo J, Sadeghi A R, et al. Efficient helper data key extractor on FPGAs[C]//Cryptographic Hardware and Embedded Systems-CHES 2008, 2008: 181-197. DOI:10.1007/978-3-540-85053-3_12.
[19] Becker G T. Robust fuzzy extractors and helper data manipulation attacks revisited: theory versus practice[J]. IEEE Transactions on Dependable and Secure Computing, 2019, 16(5): 783-795. DOI:10.1109/tdsc.2017.2762675.
[20] Dodis Y, Katz J, Reyzin L, et al. Robust fuzzy extractors and authenticated key agreement from close secrets[C]//Advances in Cryptology-CRYPTO 2006, 2006: 232-250. DOI:10.1007/11818175_14.
[21] Potey S D, Dhande P M. Error detection and correction capability for BCH encoder using VHDL[C]//2019 IEEE 5th International Conference for Convergence in Technology (I2CT). March 29-31, 2019, Bombay, India. IEEE, 2019: 1-4. DOI:10.1109/I2CT45611.2019.9033847.
[22] Bromley J. If SystemVerilog is so good, why do we need the UVM? Sharing responsibilities between libraries and the core language[C]//Proceedings of the 2013 Forum on specification and Design Languages (FDL). September 24-26, 2013, Paris, France. IEEE, 2013: 1-7.
[23] 刘登科, 刘伟, 宋贺伦, 等. 一种0.11μm SRAM PUF芯片的测试与分析[J]. 电子测量技术, 2019, 42(17): 88-94. DOI:10.19651/j.cnki.emt.1902719.
[24] Xiao K, Rahman M T, Forte D, et al. Bit selection algorithm suitable for high-volume production of SRAM-PUF[C]//2014 IEEE International Symposium on Hardware-Oriented Security and Trust. May 6-7, 2014, Arlington, VA, USA. IEEE, 2014: 101-106. DOI:10.1109/HST.2014.6855578.
[25] Liu M Q, Zhou C, Tang Q Y, et al. A data remanence based approach to generate 100% stable keys from an SRAM physical unclonable function[C]//2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED). July 24-26, 2017, Taipei, Taiwan, China. IEEE, 2017: 1-6. DOI:10.1109/ISLPED.2017.8009192.
[26] 江建国. BCH编译码器的设计及验证[D]. 上海: 上海交通大学, 2011.
[27] 张家梁, 宋贺伦. 一种基于BCH算法的SRAM PUF芯片的设计、测试与分析[J]. 电子测量技术, 2021, 44(6): 28-35. DOI:10.19651/j.cnki.emt.2105822.
[28] 奚珍珍, 刘顺兰. 一种基于BCH级联极化码的分段校验译码算法[J]. 软件导刊, 2021, 20(9): 191-195. DOI:10.11907/rjdk.202436.
[29] Shifman Y, Miller A, Keren O, et al. An SRAM-based PUF with a capacitive digital preselection for a 1E-9 key error probability[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2020, 67(12): 4855-4868. DOI:10.1109/TCSI.2020.2996772.
[30] Korenda A R, Assiri S, Afghah F, et al. An error correction approach to memristors PUF-based key encapsulation[C]//2021 IEEE International Conference on Omni-Layer Intelligent Systems. August 23-25, 2021, Barcelona, Spain. IEEE, 2021: 1-6. DOI:10.1109/COINS51742.2021.9524282.