Test Generation Based on Behavioral Model at RT-Level and Delay Testing

doi:10.7523/j.issn.2095-6134.2002.2.018

Abstract

Abstract:

The growing complexity of modern ICs is driving the trend of automatic test pattern generation (ATPG) towards testing at high level, particularly at register transfer level (RTL). At the same time, it is also more critical to perform delay testing to ensure correct temporal behavior of fast digital systems than before. This dissertation first surveys the recent development of test generation and delay testing techniques. Then, a new level of description on RTL behavioral model, termed behavioral phase clustering description, is introduced. Techniques of test generation based on behavioral phase clustering descriptions are proposed, and applied to an RTL ATPG system called ATCLUB. Experimental results show that ATCLUB reduces CPU time and test length significantly compared with other ATPG systems. This dissertation also introduces a novel method of delay testing with variable double observations. And a new approach to delay fault diagnosis based on the method is proposed. These techniques are adopted in DTwDO, a delay testing system based on variable double observations, including a ATPG tool and a fault diagnosis tool. Experimental results demonstrate a significant reduction of the number of paths to be selected to guarantee a complete delay testing, and a high rate of successful fault location.

Key words: register transfer level (RTL), finite state machine (FSM), automatic test pattern generation (ATPG), delay testing, fault diagnosis

CLC Number:

TN406

LI Hua-Wei, LI Zhong-Cheng. Test Generation Based on Behavioral Model at RT-Level and Delay Testing[J]. , 2002, 19(2): 198-201.

References

[1] Hua-Wei Li, Ying-Hua Min, Zhong-Cheng Li.IC Testing by Phase Classification Based on Behavioral Description of RTL.IEEE 1st Workshop on RTL A TPG & D FT, Changsha, 2000.104 ～ 106

[2] Hua-wei Li, Ying-hua Min, Zhong-Cheng Li.Refinement of Finite-State Machines.7th International Conf on Computer-Aided Design and Computer Graphics, Kunming, 2001.624～ 629

[3] Hua-Wei Li, Ying-Hua Min, Zhong-Cheng Li.An RT-level ATPG Based on Clustering of Circuit States.IEEE 10th Asian Test Symposium, Japan, 2001.213～ 218

[4] Hua-Wei Li, Ying-Hua Min.Efficient RT-level Test Generation Techniques based on Refinement of Finite-state Machines.IEEE 2nd Workshop on RTL A TPG & D FT, Japan, 2001.157 ～ 161

[5] Hua-Wei Li, Ying-Hua Min, Zhong-Cheng Li.A Survey on Path Delay Testing.9th Chinese Fault Tolerance Conference (CFTC-9), in Chinese, 2001.207 ～ 213 (李华伟, 闵应骅, 李忠诚.通路时延测试综述.2001 年全国容错会议, 207 ～ 213)

[6] Hua-Wei Li, Zhong-Cheng Li, Ying-Hua Min.Reduction of Number of Paths to be Tested in Delay Testing.Journal of Electronic Test-ing :Theory and Applications, 2000, 16(5):477 ～ 485

[7] Hua-Wei Li, Zhong-Cheng Li, Ying-Hua Min.Delay Testing with Double Observations.7th IEEE Asian Test Symposium。Singapore,1998.96 ～ 100

[8] Hua-Wei Li, Zhong-Cheng Li, Ying-Hua Min.Delay Testing with Duplicating Variable Observation Points.Acta Electronica Sinica, (in Chinese)1999, 27(11):120 ～ 122 (李华伟, 李忠诚, 闵应骅.双倍可变观测点的时滞测试.电子学报, 1999, 27(11):120 ～ 122)

[9] Hua-Wei Li, Zhong-Cheng Li, Ying-Hua Min.Delay Test Generation with a Time Parameter.Chinese Journal of Computers, 1999, 22(4):390～ 394 (李华伟, 李忠诚, 闵应骅.带时间参数的测试产生.计算机学报, (in Chinese)1999, 22(4):390～ 394)

[10] Hua-Wei Li, Zhong-Cheng Li, Ying-Hua Min.Single T ransition Sensitization.Journal of Computer-Aided Design &Computer Graphics,(in Chinese)2000, 12(4):308～ 211(李华伟, 李忠诚, 闵应骅.单跳变敏化.计算机辅助设计与图形学学报, 2000, 12(4):308～211)

[11] Hua-Wei Li, Zhong-Cheng Li, Ying-Hua Min.Measurement-Based Delay Fault Diagnosis.Chinese Journal of Computers, 1999, 22(11):1178 ～ 1184 (李华伟, 李忠诚, 闵应骅.基于测量的时延故障诊断.计算机学报, (in C hi nese)1999, 22(11):1178 ～ 1184)