Design and implementation of high-speed floating points FFT processor based on FPGA

doi:10.7523/j.issn.2095-6134.2015.02.016

Abstract

Abstract:

An improved parallel FFT/IFFT butterfly structure is presented. The structure, which is based on the decimation-in-time (DIT) Radix-2 algorithm, contains 8 paths in parallel. IEEE single precision floating complex FFT/IFFT processors are designed by using this parallel structure and achieved with Xilinx ISE 13.1 software. Verifications are carried out with Virtex6 FPGA of Xilinx. The results show that the FFT/IFFT processors can make use of the resources reasonably and enhance both the speed and precision of computation.

Key words: FPGA, single precision floating, FFT/IFFT, Radix-2 algorithm, parallel structure

CLC Number:

TN911

SU Bin, LIU Chang, PAN Zhigang. Design and implementation of high-speed floating points FFT processor based on FPGA[J]. , 2015, 32(2): 259-263.

References

[1] Patti A, Sezan M, Tekalp A. Super-resolution video reconstruction with arbitrary sampling lattices and nonzero aperture time[J]. IEEE Trans on Image Processing, 1997, 6(8):1 064-1 076.

[2] Sanchez M A, Garrido M, Lopez-Vallejo M, et al. Implementing FFT based digital channelized receivers on FPGA platforms[J]. Aerospace and Electronic Systems, 2008, 44(4):1 567-1 585.

[3] 李伟, 孙进平, 王俊, 等. 一种基于FPGA的超高速32K点FFT处理器[J]. 北京航空航天大学学报, 2007, 33(12): 1 440-1 443.

[4] 荣瑜, 朱恩. 一种高性能FFT蝶形运算单元的设计[J]. 东南大学学报:自然科学版, 2007,37(4):565-568.

[5] 杨靓, 黄巾, 刘红侠, 等. 一种高效的FFT处理器地址快速生成方法[J]. 信号处理, 2004(3): 251-257.

[6] Xilinx Company. LogiCORE IP Floating-Point Operator v5.0 [EB/OL]. America: Xilinx Company, (2011) [2014-02-20]. http://www.xilinx.com/products.

[7] Yang C, Chen H. A efficient design of a real-time FFT architecture based on FPGA [C]//Radar Conference, IET International. 2013:1-5.

[8] 栗旭光, 何国经, 刘江涛. 基于FPGA IP核的FFT实现与改进[J]. 电子科技,2013,26(12):96-100.

[9] DerafshiZH, Frounchi J, Taghipour H. A high speed FPGA implementation of a 1024-point complex FFT processor [C]//Computer and Network Technology, 2010 Second International Conference on. 2010:312-315.

[10] Zhou S, Wang X C, Ji J J, et al. Design and implementation of a 1024-point high-speed FFT processor based on the FPGA [C]//Image and Signal Processing, 2013 6th International Congress on. 2013:1 112-1 116.

[11] 王文芳, 周盛, 王晓春, 等. 1024点高速FFT处理器的FPGA设计与实现[J]. 国际生物医学工程杂志, 2011, 34(4):205-208.

[12] 刘健, 史彩娟, 赵丽莉. 基于FPGA的高速浮点FFT的实现研究[J]. 微型机与应用, 2012,31(14):79-84.

[13] Sun X, Qiu D L, Chen H, et al. An implementation of FFT processor [C]//Radar Conference 2013, IET International. 2013:1-4.

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