Implementation of radar monitoring and controlling system based on the SOPC of NiosII CPU

doi:10.7523/j.issn.2095-6134.2010.1.009

Abstract

Abstract:

This study presents a radar monitoring and controlling system which is mainly based on the NiosII CPU and introduces the hardware integration and software design flow of the system on programmable chip. The kernel of design is Cyclone II family FPGA which supports the 32 bits high performance NiosII CPU, and application software is developed in NiosII IDE environment tool. Compared with the traditional monitoring and controlling system, the present design has capabilities of fast data transmitting, low power consumming, and high integration.

Key words: radar monitoring and controlling system, system on programmable chip(SOPC), NiosII CPU, FPGA

CLC Number:

TN368.1

XIE Dong-Hui, QI Wei-Min. Implementation of radar monitoring and controlling system based on the SOPC of NiosII CPU[J]. , 2010, 27(1): 63-69.

[1]	ZHANG Xue, JIANG Quanjiang, LIANG Guang, YU Jinpei. Design and implementation of a generic parallel architecture for LDPC codes based on FPGA [J]. , 2020, 37(5): 714-719.
[2]	SU Bin, LIU Chang, PAN Zhigang. Design and implementation of high-speed floating points FFT processor based on FPGA [J]. , 2015, 32(2): 259-263.
[3]	YE Xi-En, ZHU Yin-Feng. Design of PCI transmission card based on pci_t32 [J]. , 2013, 30(5): 688-693.
[4]	NI Jian-Jun, LI Tao, WANG Jian-Yu. Circuit design of DDR2 SDRAM high-speed memory for space remote sensing camera simulator system [J]. , 2013, 30(5): 682-687.
[5]	WANG Jing, LIU Zhong-Sheng, DING Bin, XIANG Mao-Sheng, WEI Li-Deng, SUN Xi-Rui. Real-time data acquisition system for baseline measurements of InSAR based on PCI and FPGA [J]. , 2013, 30(1): 53-59.
[6]	QI Yong-Jun, NI Ji-Jun. Study on the real-time high precision control of large quantity displacement actuators for extremely large telescope based on FPGA [J]. , 2011, 28(5): 597-603.
[7]	CHEN Zhe, TU Guo-Fang, ZHANG Can, CHEN De-Yuan. Design of CCSDS image compression system based on FPGA [J]. , 2011, 28(1): 101-107.
[8]	CAI Xiao-Ning, CHEN Zhong-Lin, DONG Ge, XIE Shan-Ying. Optimization of digital PID controller on hardware [J]. , 2010, 27(5): 690-694.
[9]	SUN Tao, ZHANG Hua-Chun. Realization of FPGA-based MIL-STD-1553B bus remote terminals controller [J]. , 2010, 27(4): 523-529.
[10]	LI Hai-Ping, KONG Xiang-Cheng. Design and implementation of FPGA UART [J]. , 2010, 27(2): 199-203.
[11]	LI Xin-Wei, ZHANG Ping, ZHU Lei. An airborne SAR motion compensation algorithm based on array scanning and its implementation [J]. , 2010, 27(1): 70-75.
[12]	SUN Jia-Bin, YANG Hai-Gang. Design of a twisting-style switch matrix based on bus architecture [J]. , 2010, 27(1): 43-48.
[13]	YUAN Jing, LIANG Huai-Ning, LI Zao-She, YU Wei-Dong. Space-borne SAR data processing based on intermediate frequency sampling [J]. , 2009, 26(4): 497-502.
[14]	Li Lin, Guo Li, Bai Xue-fei, Huang Hao. An efficient realization of MDCT/IMDCT based on N/8-point FFT kernel [J]. , 2008, 26(6): 810-815.
[15]	YE Yong-Chen, ZHAO Guang-Heng, SU Jian. The Implementation of 1553B Bus’ Remote Terminal Based PowerPC Processor Hardcore [J]. , 2006, 23(3): 407-411.

Implementation of radar monitoring and controlling system based on the SOPC of NiosII CPU

PDF (PC)

Knowledge

Abstract

Cite this article

share this article

References

Related Articles 15

Recommended Articles

Metrics

Comments