Optimization of digital PID controller on hardware

doi:10.7523/j.issn.2095-6134.2010.5.017

Abstract

Abstract:

PID control method is widely used in the feed-back circuit of switch mode power supply. Since the analog PID controller is sensitive to temperature and electromagnetic interference, we discuss hardware implementation of digital PID controller in the present paper. With pipeline operation the efficiency of the algorithm was improved, and with signed binary fraction operation the resource cost of the circuit was reduced. Finally, this digital PID algorithm was implemented on an Actel AFS600 FPGA chip, and simulation result shows its efficiency and feasibility.

Key words: digital PID controller, FPGA, AFS600, pipeline, SBF

CLC Number:

TP273

CAI Xiao-Ning, CHEN Zhong-Lin, DONG Ge, XIE Shan-Ying. Optimization of digital PID controller on hardware[J]. , 2010, 27(5): 690-694.

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Optimization of digital PID controller on hardware

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