Circuit design of DDR2 SDRAM high-speed memory for space remote sensing camera simulator system

doi:10.7523/j.issn.2095-6134.2013.05.017

Abstract

Abstract: In order to meet the function verification requirements of the space remote sensing camera electronics system, we design a set of simulator system composed of FPGA and DDR2 SDRAM. For considering difficulties in designing DDR2 SDRAM and for improving the signal integrity, we analyze the DDR2 SDRAM impedance matching form and matching resistance location in detail and give a feasible design scheme on PCB layout and FPGA pin constraints. Experimental results show that DDR2 SDRAM works at data transmission speed of 320 Mbps/pin with either single-ended or differential clock, and the signal quality is still satisfactory.

Key words: FPGA, DDR2 SDRAM, pin constraints, space remote sensing camera simulator system

CLC Number:

NI Jian-Jun, LI Tao, WANG Jian-Yu. Circuit design of DDR2 SDRAM high-speed memory for space remote sensing camera simulator system[J]. , 2013, 30(5): 682-687.

References

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